How to use a pure FPGA to implement an embedded vision solution

January 13, 2023

Embedded vision is one of the most exciting areas of technology today.

Regarding the embedded vision application using Zynq SoC, the enthusiastic people say too much, I will not go into details. Today we take a new look at how to use a pure FPGA to implement an embedded vision solution.

This article will show you how to use the Digilent Nexys Video Artix-7 FPGA Multimedia Audio and Video Development Board to implement a simple HDMI input/output video processing system. Especially if you are a newbie, through this article, you will have a more basic understanding of FPGA-based video processing.

Frankly, the Digilent Nexys Video development board is probably the most cost-effective audio and video processing FPGA pocket lab on the market. As an evaluation board dedicated to audio and video processing teaching and prototyping of video and vision applications, the board features the most powerful Aritx-7 XC7A200T FPGA in the Xilinx Artix-7 family.

Today we will introduce how to use Nexys Video to implement a simple HDMI input/output video processing system. Let's first look at the following I/O and peripheral interfaces that are supported by this board to support video reception, processing, and generation/output:

HDMI input

HDMI output

Display output port

Ethernet

UART

USB

512MB DDRSDRAM

Line In / mic input / headphone output / line out (Line Out)

FMC

To create a simple image processing pipeline using the VHDL and RTL methods, we need to implement the following architecture:

The supervisory processor (in this case, the MicroBlaze soft-core RISC processor implemented with Xilinx Artix-7 FPGA) is used to monitor communication with the user interface and configure the image processing pipeline as required by the application. In this simple architecture of this example, the data received by the HDMI input is converted from the original parallel format video data, Hsync and VSync to AXI Streaming (AXIS) format. We want to convert the data to AXIS format because Vivado offers multiple image processing IPs that use this data format. If we use Vivado HLS to create our own image processing module, it is also important to be able to support the AXIS interface.

The MicroBlaze processor needs to support the following peripherals:

AXI UART – support system communication and control

AXI Timer – enables MicroBlaze to run events in real time

MicroBlaze Debug Module – Support for MicroBlaze debugging

MicroBlaze local storage – connected to DLMB and ILMB (data & command local storage bus)

We will use the storage interface generator to create a DDR interface that interfaces with the SDRAM on the board. This interface and SDRAM create a common storage framework that accesses the image processing pipeline and accesses the monitoring processor using AXI interconnect.

To create a simple image processing pipeline you need to use the following IP:

DVI2RGB – HDMI input IP from Digilent

RGB2DVI – HDMI output IP from Digitlent

Video In to AXI4-Stream – Convert Parallel Video Input to AXI Streaming Protocol (Vivado IP)

AXI4-Stream to Video Out – Convert AXI-Stream to Parallel Video Output (Vivado IP)

Video Timing Controller Input – Detect input video stream parameters (Vivado IP)

Video Timing Controller Output – Generate Output Video Stream Timing Parameters (Vivado IP)

Video Direct Memory Access – supports image writing and reading from DDR SDRAM

At the heart of the video processing chain is VDMA, which we use to move images into DDR memory.

The figure above shows how IP converts streaming data into memory-mapped data in read and write pipelines. Both VDMA channels provide the ability to convert between streaming data and memory mapped data. The write channel supports the conversion to the memory map and the read channel provides the memory map to the stream conversion.

When we put all of this into Vivado to create the initial base system, we got the following architecture, which is provided by the Nexys Video HDMI example.

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